Corporate Events

Advantest Corporation announced the year-end dividend of JPY 30.00 per share for the fiscal year ended March 31, 2026, payable on June 2, 2026 against JPY 20.00 per share a year ago. Record date on March 31, 2026. Total amount of dividends JPY 21,765 million. Source of dividends from Retained earnings. Reasons for Determination of Year-End Dividends: The shareholder return policy of Advantest has set a target to achieve a cumulative total return ratio of 50% or more over the three years of the third mid-term management plan with a minimum dividend of JPY 30.00 per share for annual. Based on this policy and the result of the consolidated financials for the fiscal year ended March 31, 2026, we set the year-end dividend to JPY 30.00 per share.

Advantest Corporation, Board Meeting, Apr 27, 2026. Agenda: To consider and approve the disposal of Treasury Stock as Restricted Stock.

Advantest Corporation, Board Meeting, Apr 01, 2026.

Advantest Corporation announced Pin Scale 5000B, an enhanced digital test solution for the V93000 EXA Scale Platform designed to address the growing test requirements of advanced artificial intelligence (AI) and high-performance computing (HPC) devices. AI and HPC semiconductor capabilities and complexity are growing swiftly, driven by advanced process nodes, heterogeneous integration and chiplet-based architectures. These devices require significantly higher structural and functional test coverage and processing of rapidly increasing volumes of test data. The Pin Scale 5000B card significantly expands available vector memory, offering deep and scalable storage capacity aligned with industry demands. Hardware and software facilitate optimal memory usage in chiplet-based architectures, reducing customers’ overall consumption and associated costs while addressing evolving memory requirements for the future. The new card also enables customers to efficiently scale their existing test programs and hardware configurations in response to evolving device requirements. This solution is engineered to accommodate contemporary scan fabric architectures, enabling concurrent testing of multiple IP cores using a streaming approach. Its new hardware capabilities allow test results to be observed across multiple cores within a single test pattern execution, enabling instantaneous insights into error distribution among the cores. These capabilities help improve structural coverage and core-level visibility, significantly reducing test times and cost-of-test. The Pin Scale 5000B delivers high-bandwidth test access, offering data rates up to 5 Gbps through the proven pin electronics architecture of the Pin Scale 5000. Pin Scale 5000B is a fully compatible superset of the established Pin Scale 5000, complementing the V93000 portfolio. The Pin Scale 5000B digital test instrument is now ramping with key customers.

Advantest Corporation has announced a Fixed-Income Offering. Security Name: Zero Coupon Bonds Due 2031 Security Type: Corporate Bond/Note (Convertible) Principal Amount: ¥100 billion Security Features: Convertible; Zero Coupon Coupon Type: Zero

Advantest Corporation Presents at International Semiconductor Industry Group (ISIG) Symposium 2026, Apr-21-2026 11:15 AM. Venue: Sunnyvale, California, United States. Speakers: Richard Lathrop, VP SOC Business Development.

International Semiconductor Industry Group Ltd, International Semiconductor Industry Group (ISIG) Symposium 2026, Apr 20, 2026 through Apr 21, 2026. Venue: Sunnyvale, California, United States.

Advantest Corporation announced the opening of two Advantest Innovation Centers—one located on the company’s campus in San Jose, Calif., and another currently under construction in nearby Sunnyvale, Calif. The Advantest Innovation Center is a first-of-its-kind space offering laboratories and advanced test equipment. The facilities are designed to enable deep collaboration with partners across the semiconductor value chain, accelerating the development of innovative test solutions for next-generation semiconductor technologies. The Advantest Innovation Centers provide a unique environment to support this collaboration, featuring equipment, clean rooms and the latest test technologies and test insertions for advanced packaging and complex device architectures. Strategically located in Silicon Valley, these facilities offer a central hub for hands-on innovation, enabling the company’s partners to work side by side with Advantest’s team of experts to develop innovative solutions that optimize reliability and improve productivity. Partnering early in the development process allows participants to build informed, long-term roadmaps and align R&D efforts to address industry challenges from the outset. Through these collaborations, the Advantest Innovation Centers will help deliver test solutions that innovate workflows to support the needs of customers in high-performance computing, edge AI, and other emerging markets worldwide. The Advantest Innovation Center located in San Jose is open, while the Sunnyvale location is planned to open later this summer. Partnerships have already been initiated with manufacturers and suppliers.

Advantest Corporation Presents at AServer/Cloud Computing/AI Forum, May-13-2026 . Venue: San Jose, California, United States.

JEDEC Solid State Technology Association, aServer/Cloud Computing/AI Forum, May 13, 2026. Venue: San Jose, California, United States.

Advantest Corporation Presents at AMobile/Client/Edge Forum, May-12-2026 . Venue: San Jose, California, United States.

JEDEC Solid State Technology Association, aMobile/Client/Edge Forum, May 12, 2026. Venue: San Jose, California, United States.

Advantest Corporation, 2026 Earnings Call, Apr 27, 2026

From January 1, 2026 to March 31, 2026, the company has repurchased 871,800 shares, representing 0.12% for ¥44,228.37 million. With this, the company has completed the repurchase of 2,048,700 shares, representing 0.28% for ¥67,680.2 million under the buyback announced on October 28, 2025.

Advantest Corporation, Board Meeting, Mar 31, 2026. Agenda: To consider and approve the Disposal of Treasury Stocks as Restricted Stock.

Advantest Corporation Presents at SEMICON China 2026, Mar-22-2026 through Mar-27-2026. Venue: Shanghai New International Expo Centre, Shanghai, China. Presentation Date & Speakers: Mar-22-2026, Bank Liu, Chelsea Zhou, Fangmin Chu, Ya Gao. Mar-23-2026, Bank Liu, Daniel Sun, Dong Hao, Felix Chen, Haijing Wu, Kaitao Liu, Kevin YAN, Liuhao Chen, Norris Wang, Qingchuan Ma, Qinghua Qi, Rong Tang, Ruiqiang Liu, Xiao Li, Xiaoxiao Wei, Yaqiong Mao, Ying He, Zhenyan Cao.

Advantest Corporation announced that they will report fiscal year 2026 results at 3:30 PM, Tokyo Standard Time on Apr 27, 2026

Advantest Corporation Presents at Chiplet Summit 2026, Feb-17-2026 08:30 AM. Venue: Santa Clara Convention Center, Santa Clara, California, United States. Speakers: Andreas Harder.

Advantest Corporation revised consolidated earnings guidance for the year ending March 31, 2026. For the year, the company expects the net sales to be JPY 1,070,000 million, operating income to be JPY 454,000 million, net income of JPY 328,500 million, net income attributable to owners of the parent to be JPY 328,500 million or basic earnings per share to be JPY 452.34 against net sales to be JPY 950.0 billion, operating income to be JPY 374.0 billion, net income of JPY 275.0 billion.

Advantest Corporation, Board Meeting, Jan 28, 2026. Agenda: To consider Regarding Cancellation of Treasury Shares.

Advantest Corporation, Q3 2026 Earnings Call, Jan 28, 2026

Advantest Corporation expected to report Fiscal Year 2026 results on April 24, 2026. This event was calculated by S&P Global (Created on January 7, 2026).

From October 28, 2025 to December 31, 2025, the company has repurchased 1,176,900 shares, representing 0.16% for ¥23,451.83 million. With this, the company has completed the repurchase of 1,176,900 shares, representing 0.16% for ¥23,451.83 million under the buyback announced on October 28, 2025.

Advantest Corporation, Board Meeting, Dec 18, 2025. Agenda: To dispose treasury stocks based on the post-issued restricted stock unit.

Advantest Corporation and Tokyo Seimitsu Co., Ltd. announced plans to co-develop a new die-level prober, designed for the testing of high-performance computing (HPC) devices. Semiconductors are expected to become increasingly advanced and complex in the coming years. To promptly meet evolving market needs and deliver high-performance total test solutions to customers, close collaboration across the semiconductor value chain is essential. Advantest and Tokyo Seimitsu will jointly develop die-level prober, leveraging their respective expertise to deliver advanced probing capabilities essential for testing AI and high-performance computing (H PC) devices. AI and high-performance computing ("HPC") devices, such as GPUs and CPUs used in servers, require extremely high computational performance for AI model training, inference and execution. These devices often employ advanced 2.5D/3D packaging technologies, which generate significant heat during massive data processing. As a result, controlling temperature during test is a major challenge. Through this collaboration, the two companies will strengthen next-generation probing and handling technologies to address these challenges and contribute to the growth of the AI/HPC market.

Advantest Corporation Presents at SEMICON Japan 2025, Dec-17-2025 . Venue: Tokyo Big Sight 3 Chome-11-1 Ariake, Koto City, Tokyo, Japan.

Advantest Corporation announced that they will report Q3, 2026 results on Jan 28, 2026

Advantest Corporation announced the T2000 AiR2X, a next-generation air-cooled test system engineered to meet rising demand for compact, cost-efficient testers in evaluation and high-mix, low-volume production environments. The new solution is fully compatible with the conventional T2000 test system and delivers twice the test resources of the previous air-cooled T2000 AiR test system, while maintaining low power and air-cooling requirements. The T2000 AiR2X addresses multiple converging market factors, including end-of-life support for legacy systems such as the T6500 series and T7700 series, and ongoing replacement needs across compact air-cooled testers. With a multitude of air-cooled SoC test systems in operation worldwide, the new T2000 AiR2X solution positions Advantest to meet sustained demand in this growing market. With its flexible measurement configuration, the T2000AR2X supports up to 12 measurement modules, including functional/SCAN test, high-precision DC and automotive device DC testing up to 320V. The system's unique multisite controller function significantly reduces test time during volume production. The T2000 AiR 2X incorporates Advantest's T2000 RECT550 performance board, which flexibly supports a wide range of configurations, along with a unified support infrastructure and expandable module options, adopting the same program environment used in the T2000. In addition, the Rapid Development Kit (RDK) significantly reduces the effort required for program creation and debugging, contributing to shorter platform migration and implementation times. Initial device evaluations are underway, confirming broad application coverage for the T2000 AiR2 X across industrial MCUs, consumer ASICs, battery-monitoring ICs for automotive and mobile devices, and power analog applications. The system will enter general availability later this month.

Advantest Corporation announced the M5241 Memory Handler, its next-generation handler developed to meet the performance, automation and cost-efficiency demands of emerging high-performance memory devices--particularly those used in artificial intelligence (AI) applications. First shipments of the new handler are scheduled for second quarter of calendar year 2026. Engineered as the next evolution of Advantest's memory test cell strategy, the M5241 utilizes vertical docking to integrate seamlessly with the company's latest T5801 ultra-high-speed DRAM tester and offers docking compatibility with existing testers, including the T5833, T5503HS2, and T5835, enabling customers to fully leverage their installed base. The handler's new temperature-control architecture--combined with optional active thermal control--delivers accurate, stable testing for advanced memory ICs, including those with significant self-heating, directly improving yield and reliability for customers' devices. The M5241 was developed in response to rapid growth in demand for high-bandwidth and high-capacity memory used in AI and data-center applications. The new handler strengthens Advantest's market-leading position while supporting customers' need for higher throughput, lower costs, and improved operational visibility. The new handler has already undergone internal evaluation with actual memory ICs in combination with the T5801 tester, completing validation under mass-production conditions. Multiple major memory manufacturers are preparing for adoption. The M5241 handler supports DDR5, next-gen DRAM, NAND, AI memory and other high-density memories. It features up to 512 parallel test sites with a maximum throughput of 46,000 units per hour and can accommodate temperature ranges from -40degC to +125degC (standard) or -55degC to +150degC (extended). Key benefits of the new handler include: High-precision temperature control: A new microchamber and optional active thermal control maintain stable device temperatures even under heavy self-heating loads, enabling accurate test conditions and improved yield. Enhanced maintainability and lower cost of ownership: Features such as automatic origin search and a seamless one-touch change kit shorten maintenance operations--taking a fourth of the time compared to prior workflows--red reducing downtime and operational costs. Automation-readiness for modern fabs: Compatibility with standard in-fab overhead transport and robotic systems, plus optional HM360 software, supports advanced automation, data visualization, and predictive maintenance.

SEMI, SEMICON China 2026, Mar 22, 2026 through Mar 27, 2026. Venue: Shanghai New International Expo Centre,, Shanghai, China.

Semper Technologies, Chiplet Summit 2026, Feb 17, 2026 through Feb 19, 2026. Venue: Santa Clara Convention Center, Santa Clara, California, United States.

Advantest Corporation Presents at SEMICON EUROPA 2025, Nov-18-2025 . Venue: Messe München, Munich, Germany.

Advantest Corporation Presents at Advanced Packaging Conference, Nov-19-2025 04:20 PM. Venue: ICM Munich, Munich, Germany. Speakers: Fabio Pizza, business segment manager, Advantest Europe.

SEMI, Advanced Packaging Conference, Nov 19, 2025. Venue: ICM Munich, Munich, Germany.

Advantest's IR Fireside Chat Q&A

Advantest Corporation announced the MTe power test platform. The cutting-edge MTe redefines test efficiency and scalability to address test requirements for the fast-growing power semiconductor market. Increasing market demand for electrification across automotive, industrial, renewable energy, telecommunication and data infrastructure applications is pushing semiconductor manufacturers to achieve higher performance and lower cost of test (CoT). The MTe platform responds to these needs by combining modular hardware architecture, ultimate system scalability and advanced digital control, redefining the standard in power semiconductor test performance and efficiency. Designed with Advantest technology, MTe provides significant footprint reduction and optimized resource distribution without performance degradation--a key enabler to attract major IDM and OSAT players. The MTe platform is able to address emerging wide-bandgap semiconductor (e.g., SiC and GaN) challenges, as well as the integration of digital IP cores on power devices (e.g., IPM and IPD), providing high bandwidth capture, best-in-class gate driver control, dynamic (and short-circuit) test up to 10kA, and flexible high-voltage digital capabilities. Aligned with Advantest's history of providing scalable test platforms, MTe distributed computing architecture provides significant multisite test efficiency, enabling a high-parallel-test solution with optimized throughput. The MTe platform is now available worldwide. Early evaluations by customers in automotive and industrial power applications have confirmed significant productivity and throughput gains compared with legacy testers.

Advantest Corporation announced that the Board of Directors resolved to make the interim dividends for the fiscal year ending March 31, 2026 of JPY 29.00 per share as compared to JPY 19 per share paid a year ago. Record date is September 30, 2025. Effective date is December 1, 2025.

Advantest Corporation revised consolidated earnings guidance for the year ending March 31, 2026. For the year the company now expects the Net Sales of JPY 950,000 million, Operating income of JPY 374,000 million, Net income of JPY 275,000 million, Basic earnings per share of JPY 378.06 as compared to previous guidance of Net Sales of JPY 835,000 million, Operating income of JPY 300,000 million, Net income of JPY 221,500 million, Basic earnings per share of JPY 302.71. In CY2025, the semiconductor industry growth is likely to continue to be driven by AI-related semiconductors. In the semiconductor tester industry, tester demand is expected to exceed the previous year’s level, driven by factors such as the increasing complexity and enhanced performance, as well as rising production volumes of AI-related semiconductors. Based on this outlook and the progress made for the six-month period ended September 30, 2025, Advantest has revised its full-year consolidated earnings forecast for the current fiscal year as shown above. .

Advantest Corporation expected to report Q3 2026 results on January 28, 2026. This event was calculated by S&P Global (Created on October 28, 2025).

Advantest Corporation (TSE:6857) announces a share repurchase program. Under the program, the company will repurchase up to 18,000,000 shares, representing 2.47% of outstanding shares for ¥150,000 million. The company will repurchase its shares for the purpose of shareholder returns and for improving capital efficiency. The program will expire on October 28, 2026. As of September 30, 2025, the company had 727,392,176 shares in outstanding and 38,749,080 shares in treasury.

The Board of Directors of Advantest Corporation has authorized a buyback plan on October 28, 2025.

Advantest Corporation, Board Meeting, Oct 28, 2025. Agenda: To consider regarding Disposal of Treasury Stock based on the Post-issued Restricted Stock Unit Plan.

Advantest Corporation, VOICE 2026 Developer Conference, May 18, 2026 through May 20, 2026. Venue: Scottsdale, Arizona, United States.

Advantest America announced it is reinventing semiconductor testing with the power of real-time artificial intelligence (AI). Advantest is combining advanced machine learning (ML) from NVIDIA with the Advantest Cloud Solutions Real-Time Data Infrastructure (ACS RTDI™?) to drive a shift from traditional test workflows to adaptive AI-driven systems. NVIDIA has selected ACS RTDI for high-volume production to power its latest AI-enabled applications for Blackwell and next-generation devices --aiming to deliver breakthrough efficiency, reduced costs, and improved yields. Testing has long been the cornerstone of chip manufacturing, ensuring every device meets exacting standards of quality and performance. Traditionally, this required weeks of data collection, fault analysis, and test deployment cycles. ACS RTDI moves testing from validation to prediction--transforming semiconductor production into an AI-driven, continuously adaptive process. Integrated with NVIDIA AI inference, ACS RTDI could bring real-time intelligence to semiconductor testing. For NVIDIA Blackwell and future devices, massive data streams are ingested through ACS Data-Feed-Forward cross-insertion, where GPU-accelerated compute optimizes the test set for every chip. This scalable GPU architecture expands seamlessly, supporting the concurrent training of multiple ML models--enabling non-stop operation to drive yield gains, dynamically optimized test coverage, and sharp reductions in latency, power, and cost. Scaling AI Across Production: ACS RTDI has demonstrated its robustness at high-volume production sites worldwide, securely supporting AI/ML-driven test automation across diverse applications. Its flexible architecture --separating data preparation, algorithms, and decisioning--empowers manufacturers to rapidly adapt as production needs evolve. Advantest also plans to incorporate NVIDIA's NeMo and NVIDIA NIM microservices into ACS semiconductor test analytics solutions. These technologies will curate heterogeneous production data, evaluate models, and deploy AI agents capable of running generative AI applications directly in the test environment. Through this integration, Advantest is setting the stage for the next wave of semiconductor innovation --where AI not only accelerates the chip development process but also transforms how such chips are tested, validated, and delivered to market.

Advantest Corporation will feature its latest semiconductor test solutions at SEMICON West 2025, which will be held from Oct. 7-9 at the Phoenix Convention Center in Phoenix, Ariz. Advantest will highlight its broad portfolio of test technologies for applications, including AI and high-performance computing (HPC), 6G, automotive and memory. Additionally, the company is a proud sponsor of this year's Test Vision Symposium and Workforce Development program and will continue its participation in SEMI's Semiconductor Climate Consortium (SCC) as one of the founding members. Product and Solution Highlights: AI/HPC device test solutions, including the V93000 EXA Scale SoC test system, the HA1200 die-level operator with unique active thermal control technology, and the T5801 Ultra-High-Speed DRAM test system, engineered to support the latest advancements in high-speed memory technologies - including GDDR7, LPDDR6, and DDR6. SiConic™?, a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. Advantest's System-Level Test platforms that achieve cost-effective structural test coverage (SCAN, MBIST,LBIST, etc.) over functional high-speed IO interface with a wide range of Active Thermal Control options, including the new 7038 Single Test Rack (STR) that offers system-level and burn-in solutions at a lower cost and smaller footprint ideal for devices with higher power and larger package sizes. Extending the V93000 test system's capabilities to support high-volume production of silicon photonics and co-packaged optics devices via a partnership with FormFactor. ACS Real-Time Data Infrastructure (ACS RTDI™?), a solution platform that automates the process of converting insights into actionable production steps within the same test insertion in milliseconds, optimizing yield, improving quality and reducing time to market. CREA's power semiconductor test equipment for a wide variety of power devices, including SiC and GaN power testing on wafer, single-die, substrate, PKG, and module, typically used in industrial and automotive applications. T2000 SoC test systems with Rapid Development Kit (RDK) for all SoCs, including automotive and power analog, and IP Engine 4A test solutions for the fastest image processing to reduce CIS testing time and costs. In addition to its product display, Advantest will participate in this year's Test Vision Sym Symposium from Oct. 8-9. Advantest will deliver multiple presentations on a myriad of relevant topics, including advanced packaging, data analytics, the utilization of AI/ML in test, co-packaged optics and silicon photonics. Please refer to the session program for more details.

Advantest Corporation, Q2 2026 Earnings Call, Oct 28, 2025

Advantest Corporation launched its new Advantest Power Optimization Solution (APOS) for the V93000 system-on-chip (SoC) test platform. Designed to improve energy efficiency without compromising performance, the APOS software enables foundries and outsourced semiconductor assembly and test (OSAT) providers to achieve their sustainability goals while reducing operational costs. With energy consumption representing a significant operational expense, semiconductor companies are actively seeking ways to optimize power usage. Developed by Advantest's production service team, APOS provides a comprehensive power-saving framework, allowing users to visualize and manage V93000 tester power consumption in real time, helping to lower electricity costs while maintaining high throughput and test accuracy. In addition, APOS contributes to corporate sustainability efforts by improving tester energy efficiency and thereby reducing the overall carbon footprint. The APOS software has already been installed on V93000 test systems at multiple customer sites, yielding positive results in reducing test costs and strengthening environmental initiatives. Smart power management - APOS expands Advantest's Smart TestCell (STC) ecosystem, which leverages advanced automation and resource management to enable smart semiconductor manufacturing. APOS automatically enables/disables selected test cards based on real-world tester scenarios, reducing unnecessary power consumption. Real-time visualization - APOS Client Display provides an intuitive dashboard with real-time insights into power usage and card type, status and quantity used. Centralized control and reporting - The APOS Dashboard integrates with the Testcell Central System (TCS) Server Web Dashboard to centrally manage test-floor power-saving data and utilizes the history record for reporting and further optimization. The Advantest Power Optimization solution for the V93000 test platform is available now to the global market.

The company closed its plan on September 22, 2025.

From July 1, 2025 to September 22, 2025, the company has repurchased 4,431,100 shares, representing 0.61% for ¥54,553.15 million. With this, the company has completed the repurchase of 6,643,900 shares, representing 0.91% for ¥69,999.94 million under the buyback announced on April 25, 2025.

Advantest Corporation Presents at 2025 International Test Conference, Sep-21-2025 through Sep-26-2025. Venue: Hilton San Diego Bayfront, San Diego, California, United States. Presentation Date & Speakers: Sep-23-2025, Ira Leventhal, Vice President of research and venture. Sep-24-2025, Frank Mielke, Solution Architect R&D, Ira Leventhal, Vice President of research and venture.

IEEE Computer Society Inc., 2025 International Test Conference, Sep 21, 2025 through Sep 26, 2025. Venue: Hilton San Diego Bayfront, San Diego, California, United States.

Advantest Corporation announced its 7038 Single Test Rack (STR) system-level test (SLT) and burn-in test (BI) solution. The 7038 STR extends the company's proven 7038 SLT platform with a lower-cost architecture optimized for slot-based automated test solutions, enabling right-sized SLT deployment in the production of artificial intelligence (AI), high-performance compute (HPC), automotive, and other low- to mid-volume devices. The new 7038 STR delivers liquid-cooled thermal management of up to 1.4 kW per test site, enabling robust testing of today's most complex and power-hungry devices. Like the 7038 dual-rack test solution, the 7038 STR will also offer air-cooled thermal management for even more cost-effective test. With asynchronous test capability for up to 48 sites, the system offers a single-vendor turnkey solution that includes socket interface boards (SIBs), sockets, device multi-zone thermal management, software management and control, and an integrated automated handler. This single-source approach eliminates the need to obtain multiple components from different suppliers, streamlining deployment and reducing risk for customers. As device complexity and power requirements continue to rise in the HPC, AI, and automotive markets, the need for advanced SLT and BI solutions has grown significantly. In particular, automotive makers investing heavily in advanced driver assistance systems (ADAS) and telematics processing need a mid-power solution that goes beyond air-cooled thermal solutions for SLT. The 7038 STR provides a solution that can scale with the power and size increase of these processors. Air-cooled systems are limited to approximately 100 W per device, while the 7038 STR's liquid-cooled design supports the higher power levels demanded by next-generation processors with future upgrade capabilities exceeding 1.4 kW. "The 7038 STR represents the next evolution of system-level and burn-in test portfolio. The 7038 STR is especially suited for mid- to low-volume production environments where customers require advanced SLT/BI capabilities without the higher investment and larger footprint of dual-rack systems. Its compatibility with the broader 7038 product family means that customers can easily migrate test programs and hardware between the single- and dual-rack configurations as their production volumes grow. In addition, the system is fully compatible with ATS ActivATE360™?, Advantest's intuitive test management software. ActivATE provides turnkey real-time monitoring, logging, and control across device temperature, current, and power, simplifying program development and ensuring smooth integration into customer test environments. The 7038 Single Test Rack solution is available immediately, with pricing dependent on slot configuration, sites per slot, and thermal requirements.

Advantest Corporation announced that they will report Q2, 2026 results on Oct 28, 2025

Advantest Corporation announced the release of its next-generation CD-SEM* E3660, engineered for the dimensional metrology of photomasks and EUV masks used in cutting-edge semiconductor manufacturing. Compared to the previous generation's E3650, the E3660 delivers more than a 20% improvement in CD reproducibility, enabling process engineers to meet the stringent requirements of mask manufacturing at the 2nm node and beyond. By reinforcing lithography process control in advanced device fabrication, the E3660 furthers Advantest's vision of providing holistic test solutions across the semiconductor value chain. In semiconductor device fabrication, continuous scaling and pattern complexity are driving a sharp increase in lithographic hotspots--locations where multi-patterning and pattern transfer become particularly error-prone. Masks used to form wafer circuitry are evolving, with higher layer counts and more intricate geometries. This, in turn, has significantly increased the number of required metrology sites, demanding measurement systems with both higher throughput and superior reproducibility. The industry is also transitioning toward curvilinear mask patterns, enabled by advances in multi-beam mask writing and high-performance computing. These patterns are expected to see large-scale deployment around 2027 with the adoption of High Numerical Aperture EUV lithography in device production. To ensure design-to-mask fidelity under these conditions, CD-SEMs must not only provide highly reproducible critical dimension measurements but also generate SEM images with greater fidelity to true pattern contours. Moreover, metrology solutions must evolve to incorporate curvature-sensitive algorithms capable of quantifying deviations between complex mask features and original design intent. Leading up to the development of the E3660, Advantest has collaborated with imec, to validate the correlation of CD-SEM results obtained from the "E3650" with those from Advantest's previous generation CD-SEMs and EDA-based reference data. This enabled Advantest to improve metrology reliability and work with imec to advance the development and validation of new measurement techniques for curvilinear geometries. The E3660 platform reflects the outcome of this collaboration, achieving the reproducibility required for 2nm node mask manufacturing, enabling high-throughput measurement to handle increasing site counts, and providing unique measurement functions for curvilinear patterns. By integrating these capabilities, the E3660 is positioned to deliver robust metrology support for the next generation of mask R&D and production environments. Advantest will initially target the E3660 for deployment at Merchant Mask Shops, where commercial mask manufacturers produce masks for external customers, and Captive Mask Shops, which are in-house mask production facilities of semiconductor manufacturers. This activity establishes the E3660 as a core evaluation tool for advanced mask development and production qualification. Critical Dimension Scanning Electron Microscope: an electron microscope specialized for high-precision measurement of fine pattern dimensions on semiconductor wafers and masks.

Advantest Corporation Presents at SEMICON Taiwan 2025, Sep-09-2025 . Venue: 701F, 7F, TWTC Nangang Exhibition Hall No.1, Jingmao 2nd Rd., Nangang District, Taipei, Taiwan.

Advantest Corporation will present its latest test solutions at SEMICON Taiwan 2025 on Sept. 10-12 at the TaiNEX 1 & 2 in Taipei. At this year's SEMICON Taiwan, Advantest will present innovative, sustainable test technology guided by its new corporate vision, "Be the most trusted and valued test solution company in the semiconductor value chain." Moreover, Advantest's Taiwanese subsidiary will commemorate its 30th anniversary, celebrating decades of service to Taiwan's rapidly growing semiconductor market.

Advantest Corporation Presents at SEMICON India 2025, Sep-02-2025 . Venue: Yashobhoomi India International Convention and Expo Centre, New Delhi, Delhi, India. Speakers: Koichi Tsukui, President, Group COO, Senior Executive Officer & Representative Director.

Advantest Corporation will showcase its latest memory test systems and solutions at the Future of Memory and Storage 2025 (formerly known as Flash Memory Summit) on Aug. 5-7 at the Santa Clara Convention Center in Santa Clara, California. Advantest is a gold sponsor of the event. Product Highlights: Advantest's booth #634 will be in Hall B of the convention center. The company will feature its end-to-end memory test solutions for testing next-generation memory chips, such as high-bandwidth memory (HBM), DRAM, NAND flash, non-volatile memory (NVM) and protocol storage devices. Advantest will also highlight its new T5801 ultra-high-speed DRAM test system that supports the latest advancements in high-speed memory technologies, including GDDR7, LPDDR6, and DDR6.

Advantest Corporation provided consolidated earnings guidance for the fiscal year ending March 31, 2026. For the period, the company expected net sales of JPY 835,000 million, operating income of JPY 300,000 million, net income attributable to owners of the parent of JPY 221,500 million and basic earnings per share of JPY 302.71.

Advantest Corporation, Board Meeting, Jul 29, 2025. Agenda: To consider the Notice regarding Disposal of Treasury Stock based on the Post-issued Restricted Stock Unit Plan.

Advantest Corporation, Q1 2026 Earnings Call, Jul 29, 2025

Advantest Corporation expected to report First-Half, 2026 results on October 27, 2025. This event was calculated by S&P Global (Created on July 2, 2025).

From April 25, 2025 to June 30, 2025, the company has repurchased 2,212,800 shares, representing 0.3% for ¥15,446.79 million. With this, the company has completed the repurchase of 2,212,800 shares, representing 0.3% for ¥15,446.79 million under the buyback announced on April 25, 2025.

Advantest Corporation, Board Meeting, Apr 25, 2025. Agenda: To consider Status of Share Repurchase.

Advantest Corporation announced that they will report Q1, 2026 results at 9:00 AM, Tokyo Standard Time on Jul 29, 2025